Generation of a stable reference clock frequency from a base clock frequency that may vary depending on source

ABSTRACT

A clock signal generator within an electronic device locally generates a reference clock signal having a reference frequency from a base clock signal having a base frequency. The base clock signal is from a base signal source that is external to the electronic device, and the base frequency of the base clock signal may vary depending on the base signal source. The present invention includes a plurality of frequency dividers which are coupled to the base signal source. Each of the frequency dividers outputs a divided clock signal having a respective frequency that is the base frequency divided by a respective factor. A multiplexer accepts the value of the base frequency of the base clock signal as stored within a storage device that is external to the electronic device. The multiplexer then selects as the reference clock signal a divided clock signal having a respective frequency that is closest to the reference frequency depending on the value of the base frequency. In this manner, a reference clock signal having a stable reference frequency is generated for the electronic device despite possible variations in the base frequency of the base clock signal. The present invention may be used to particular advantage when the electronic device is an Ethernet computer network peripheral device coupled between a computer host system and a computer network, and when the base signal source is from the computer host system.

TECHNICAL FIELD

This invention relates to clock signal generators, and moreparticularly, to generating a reference clock signal having a stablereference clock frequency for an electronic device from a base clocksignal having a base clock frequency that may vary depending on the baseclock signal source which is external to the electronic device.

BACKGROUND OF THE INVENTION

The present invention will be described with an example application foran Ethernet computer network peripheral device which couples a hostcomputer system to a network of computers. In this example application,the Ethernet computer network peripheral device locally generates areference clock frequency from a base clock frequency provided by thehost computer system or the network of computers. However, from thisexample application, it should be appreciated by one of ordinary skillin the art of electronic systems design that the present invention maybe used for locally generating a reference clock frequency at anyelectronic device from a base clock frequency provided by any base clocksignal source that is external to the electronic device.

Referring to FIG. 1, a network of computers 100 includes a firstcomputer 102, a second computer 104, a third computer 106, and a fourthcomputer 108 interconnected to each other via a linking network 110. Acomputer peripheral device 112 is within the first computer 102 toprovide added functionality to the first computer 102. For example, thiscomputer peripheral device 112 may be an Ethernet computer networkperipheral device which allows the first computer 102 to communicatewith the other computers 104, 106, and 108 via the linking network 110.

Such a computer peripheral device 112 includes timers for timing eventsof data transmission and reception and other types of events at thefirst computer 102 or at other parts of the network of computers 100.These timers require a respective reference clock signal having arespective reference frequency for timing such events. For example, anEthernet computer network peripheral device may require a 1 MHZ(megahertz) reference clock signal for a 1 μs (microsecond) timer and a10 MHZ reference clock for a 0.1 μs timer.

Although the computer peripheral device 112 needs reference clocksignals for timing events, original clock signal generators may becostly to incorporate within the computer peripheral device 112. Thehost system of the first computer 102 typically has a base clock signalhaving a base frequency. Moreover, other parts of the network ofcomputers 100 including the second computer 104, the third computer 106,the fourth computer 108, and the linking network 110 may include arespective base clock signal having a base frequency. Thus, it would bedesirable to generate the reference clock signals for use within thecomputer peripheral device 112 from a base clock signal alreadyavailable from a base clock signal source that is external to thecomputer peripheral device 112.

SUMMARY OF THE INVENTION

Accordingly, a primary object of the present invention is to generate areference clock signal having a reference frequency for an electronicdevice from a base clock signal having a base frequency from a baseclock signal source that is external to the electronic device. Becausethe base clock signal source is external to the electronic device, thebase frequency of the base clock signal may vary depending on the baseclock signal source. Thus, another object of the present invention is togenerate a reference clock signal having a stable reference frequencyeven when the base frequency of the base clock signal may vary.

In a general aspect of the present invention, a clock signal generatorgenerates a reference clock signal having a reference frequency for anelectronic device from a base clock signal having a base frequency. Theclock signal generator includes a first input coupled to a base signalsource that is external to the electronic device for accepting the baseclock signal from the base signal source. The clock signal generatoralso includes a second input coupled to a storage device that isexternal to the electronic device for accepting the value of the basefrequency from the storage device. Furthermore, the clock signalgenerator includes a plurality of frequency dividers. Each frequencydivider is coupled to the first input for dividing the base frequency ofthe base clock signal by a respective factor to generate a respectivedivided clock signal having a respective frequency. A multiplexer,coupled to the second input and to the plurality of frequency dividers,selects as the reference clock signal a divided clock signal having arespective frequency that is closest to the reference frequency from theplurality of divided clock signals.

The present invention may be used to particular advantage for generatingreference clock signals for timing events within an Ethernet computernetwork peripheral device coupled between a computer host system and acomputer network. In that case, the base signal source may be from thecomputer host system or the computer network, and the storage devicecontaining the value of the base frequency may be an EEPROM within thecomputer host system or the computer network.

In other aspects of the present invention, a storage device clock signalis also generated from the base clock signal for reading the value ofthe base frequency from the storage device.

These and other features and advantages of the present invention will bebetter understood by considering the following detailed description ofthe invention which is presented with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a network of computers having a computer which includes acomputer peripheral device that uses reference clock signals for timingevents;

FIG. 2, including FIG. 2A and FIG. 2B, shows the computer peripheraldevice of FIG. 1 coupled to a base signal source and a storage devicewhich are external to the computer peripheral device, according topreferred embodiments of the present invention;

FIG. 3 shows components of the computer peripheral device of FIGS. 1 and2 for generating reference clock signals from a base clock signal,according to a preferred embodiment of the present invention; and

FIG. 4 shows additional components of the computer peripheral device ofFIG. 3 for generating a storage device clock signal from the base clocksignal, according to another preferred embodiment of the presentinvention.

The figures referred to herein are drawn for clarity of illustration andare not necessarily drawn to scale. Elements having the same referencenumeral in FIGS. 1-4 refer to the same element.

DETAILED DESCRIPTION

Referring to FIG. 1, the computer peripheral device 112 of the firstcomputer 102 in the network of computers 100 requires a reference clocksignal having a reference frequency for timing events. For example, thecomputer peripheral device 112 may be an Ethernet computer networkperipheral device which requires a reference clock signal for timingtransmission and reception of data packets between the first computer102 and the rest of the network of computers 100.

Instead of including an original clock signal source, which may becostly, within the computer peripheral device 112, a base signal sourcewhich is external to the computer peripheral device 112 provides a baseclock signal having a base frequency to the computer peripheral device112. Referring to FIG. 2A, this base signal source 202 may be part ofthe host system of the first computer 102 having the computer peripheraldevice. A storage device 204 such as an EEPROM (Electronically ErasableProgrammable Read Only Memory) which is also part of the host system ofthe first computer 102 stores information regarding the base clocksignal such as the base frequency of the base clock signal. The basesignal source 202 and the storage device 204 are coupled to the computerperipheral device 112 via any type of bus interface between a computerhost system and a computer peripheral device as is known to one ofordinary skill in the art.

Referring to FIG. 2B, in an alternative embodiment of the presentinvention, the base signal source 202 and the storage device 204 mayalternatively be part of the rest of the computer network 206 includingthe second computer 104, the third computer 106, the fourth computer108, or the linking network 110 of FIG. 1. In this embodiment also, thebase signal source 202 and the storage device 204 are coupled to thecomputer peripheral device 112 via any type of bus interface between acomputer peripheral device and a network of computers as is known to oneof ordinary skill in the art.

Referring to FIG. 3, a clock signal generator 300 of the presentinvention generates a reference clock signal locally within the computerperipheral device 112 given a base clock signal from the base signalsource 202 that is external to the computer peripheral device 112. Theclock signal generator 300 includes a first input 302 coupled to thebase signal source 202 for accepting the base clock signal from the basesignal source 202. For the example of the Ethernet computer networkperipheral device, two reference clock signals may be required fortiming events. A first reference clock signal may be needed to have afirst reference frequency of 1 MHZ for a 1 μs (microsecond) timer and asecond reference clock signal may be needed to have a second referencefrequency of 10 MHZ for a 0.1 μs (microsecond) timer.

Typical base frequencies of the base clock signal from the base signalsource 202 are 2.5 MHZ, 20 MHZ, 25 MHZ, or 33 MHZ. The base frequency ofthe base clock signal may vary depending on the base signal source 202.For example, for the Ethernet computer network peripheral device 112 ofFIG. 1, the base signal source 202 of FIG. 2A from the host system ofthe first computer 102 may vary depending on the type of the host systemof the first computer 102. Furthermore, the type of computer withinwhich the computer peripheral device 112 is installed may vary with timeas computer technology advances with time.

In the case the base signal source is from the rest of the computernetwork 206 as in FIG. 2B, the base frequency may vary depending onwhich component within the computer network includes the base signalsource 202. Furthermore, this base frequency of the base clock signalmay vary with time as computer network technology also advances withtime.

To account for variability of the base frequency of the base clocksignal, the clock signal generator 300 includes a second input 304coupled to the storage device 204 for accepting information regardingthe base clock signal from the storage device 204. In particular, thesecond input 304 accepts the value of the base frequency of the baseclock signal from the storage device 204.

Then, to generate a reference clock signal having a stable referencefrequency, the clock signal generator 300 includes a plurality offrequency dividers including a first frequency divider 311, a secondfrequency divider 312, a third frequency divider 313, a fourth frequencydivider 314, a fifth frequency divider 315, a sixth frequency divider316, and a seventh frequency divider 317 in FIG. 3. Each frequencydivider outputs a respective divided clock signal having a respectivefrequency which is the base frequency divided by a respective factor.

Thus, the first frequency divider 311 generates a first divided clocksignal having a respective frequency which is the base frequency dividedby 2. The second frequency divider 312 generates a second divided clocksignal having a respective frequency which is the base frequency dividedby 2.5. The third frequency divider 313 generates a third divided clocksignal having a respective frequency which is the base frequency dividedby 3.3. The fourth frequency divider 314 generates a fourth dividedclock signal having a respective frequency which is the base frequencydivided by 20. The fifth frequency divider 315 generates a fifth dividedclock signal having a respective frequency which is the base frequencydivided by 25. The sixth frequency divider 316 generates a sixth dividedclock signal having a respective frequency which is the base frequencydivided by 33. The seventh frequency divider 317 generates a seventhdivided clock signal having a respective frequency which is the basefrequency divided by 0.25.

A multiplexer 320 is coupled to the outputs of the plurality offrequency dividers 311, 312, 313, 314, 315, 316, and 317 and to thesecond input 304. From the value of the base frequency of the base clocksignal at the second input 304, the multiplexer 320 selects as thereference clock signal a divided clock signal having a respectivefrequency that is closest to the reference frequency from the pluralityof divided clock signals.

For example, the computer peripheral device 112 may be an Ethernetcomputer network peripheral device which requires a first referenceclock signal having a first reference frequency of 1 MHZ for a 1 μs(microsecond) timer and a second reference clock signal having a secondreference frequency of 10 MHZ for a 0.1 μs (microsecond) timer.Furthermore, assume for example that the base clock signal has a basefrequency of 33 MHZ.

In that case, the second input 304 indicates to the multiplexer 320 thatthe value of the base frequency is 33 MHZ. The multiplexer then selectsthe divided clock signal from the sixth frequency divider 316 for thefirst reference clock signal of 1 MHZ at a first output 322 and selectsthe divided clock signal from the third frequency divider 313 for thesecond reference clock signal of 10 MHZ at a second output 324.

The multiplexer 320 keeps track of the respective frequency divisionfactor of each of the plurality of frequency dividers 311, 312, 313,314, 315, 316, and 317. Then, from the value of the base frequency atthe second input 304, the multiplexer 320 selects as a reference clocksignal the appropriate divided clock signal from the plurality offrequency dividers. The multiplexer 320 may include a data processor, asis typically used in an Ethernet computer network peripheral device, fordetermining a ratio of the base clock frequency over the reference clockfrequency. The multiplexer 320 then selects the output of the frequencydivider having a respective frequency division factor that is closest tothe ratio of the base clock frequency over the reference clockfrequency.

Referring to FIG. 4, in another embodiment of the present invention, theclock signal generator of the present invention may further include astorage device clock generator 400 for generating a storage device clocksignal having a storage device frequency from the base clock signal. Thestorage device clock signal drives the storage device 204 of FIG. 2 whenthe value of the base frequency is read from the storage device 204.

The storage device clock signal generator 400 is coupled to the firstinput 302 for receiving the base clock signal from the base signalsource 202 and to the second input 304 for receiving the value of thebase frequency of the base clock signal. The base clock signal iscoupled through a second plurality of frequency dividers including afirst frequency divider 401, a second frequency divider 402, a thirdfrequency divider 403, and a fourth frequency divider 404 in FIG. 4.Similar to the clock signal generator 300 of FIG. 3, each of the secondplurality of frequency dividers of FIG. 4 outputs a respective dividedclock signal having a respective frequency which is the base frequencyof the base clock signal divided by a respective factor.

Thus, the first frequency divider 401 generates a first divided clocksignal having a respective frequency which is the base frequency dividedby 4. The second frequency divider 402 generates a second divided clocksignal having a respective frequency which is the base frequency dividedby 32. The third frequency divider 403 generates a third divided clocksignal having a respective frequency which is the base frequency dividedby 40. The fourth frequency divider 404 generates a fourth divided clocksignal having a respective frequency which is the base frequency dividedby 52.

A second multiplexer 410 is coupled to the outputs of the secondplurality of frequency dividers 401, 402, 403, and 404 and to the secondinput 304. From the value of the base frequency of the base clock signalat the second input 304, the second multiplexer 410 selects as thestorage device clock signal a divided clock signal having a respectivefrequency that is closest to the storage device frequency from theplurality of divided clock signals from the second plurality offrequency dividers.

When the computer peripheral device 112 initializes, the appropriatevalue of the base frequency of the base clock signal is unknown sincethe appropriate storage device clock signal is not yet generated.Typically, storage devices such as EEPROMs are slow devices running atlow clock frequencies. Thus, at initialization, the second multiplexer410 selects the divided clock signal having a respective frequency thatis lowest of the plurality of divided clock signals of the secondplurality of frequency dividers 401, 402, 403, and 404. In FIG. 4, theoutput of the fourth frequency divider 404 which has a divided clockfrequency with a respective frequency that is the base frequency dividedby 52 is selected by the second multiplexer 410 during initialization ofthe computer peripheral device 112.

Then, once the value of the base frequency of the base clock signal isread from the storage device 202, the second multiplexer 410 selects asthe storage device clock signal a divided clock signal have a respectivefrequency that is closest to the storage device frequency from theoutputs of the second plurality of frequency dividers 401, 402, 403, and404. This storage device clock signal is coupled to the storage device202 and drives the storage device 202 for continuously reading the valueof the base frequency of the base clock signal from the storage device202.

In this manner, a reference clock signal having a reference frequency isgenerated locally within the computer peripheral device 112 given a baseclock signal having a base frequency from a base signal source which isexternal to the computer peripheral device 112. This base signal sourcemay vary and thus the base frequency of the base clock signal may vary.The present invention uses a plurality of frequency dividers and amultiplexer to generate a reference clock signal having a stablereference frequency despite possible variations in the base frequency ofthe base clock signal.

The foregoing is by way of example only and is not intended to belimiting. For example, the present invention may be implemented with anynumber of frequency dividers having any frequency division factor, andthe present invention may generate any number of reference clocksignals. More importantly, the reference clock frequency may begenerated for any electronic device (aside from just the example of theEthernet computer network peripheral device 112) from a base clocksignal provided by a base signal source disposed on any unit (aside fromjust the example of the computer host system 102 or the network ofcomputers 206) external to the electronic device, and the value of thebase frequency of the base clock signal may be read from any kind ofstorage device disposed on any unit external to the electronic device.The invention is limited only as defined in the following claims andequivalents thereof.

We claim:
 1. A clock signal generator that generates a reference clocksignal having a reference frequency for an electronic device from a baseclock signal having a base frequency, the clock signal generatorcomprising:a first input, coupled to one of a variety of a base signalsource that is external to the electronic device, for accepting the baseclock signal from the base signal source, wherein said base frequency ofsaid base clock signal is variable depending on said one of said varietyof said base signal source to which said first input is coupled; asecond input, coupled to a storage device that is external to theelectronic device, for accepting the value of the base frequency fromthe storage device, said storage device corresponding to said one ofsaid variety of said base signal source to which said first input iscoupled; a plurality of frequency dividers, each frequency dividercoupled to the first input for dividing the base frequency of the baseclock signal by a respective factor to generate a respective dividedclock signal having a respective frequency; and a multiplexer, coupledto the second input and to the plurality of frequency dividers, toselect as the reference clock signal a divided clock signal having arespective frequency that is closest to the reference frequency from theplurality of divided clock signals.
 2. The clock signal generator ofclaim 1, wherein a first reference clock signal having a first referencefrequency and a second reference clock signal having a second referencefrequency are generated by the multiplexer selecting as the firstreference clock signal a first divided clock signal having a firstrespective frequency that is closest to the first reference frequency,and by the multiplexer selecting as the second reference clock signal asecond divided clock signal having a second respective frequency that isclosest to the second reference frequency.
 3. The clock signal generatorof claim 1, further comprising:a storage device clock signal generator,coupled to the first input, the second input, and the storage device,for generating a storage device clock signal having a storage devicefrequency from the base clock signal for reading the value of the basefrequency from the storage device.
 4. The clock signal generator ofclaim 3, wherein the storage device clock signal generator furtherincludes:a second plurality of frequency dividers, each of the secondplurality of frequency dividers coupled to the first input for dividingthe base frequency of the base clock signal by a respective factor togenerate a respective divided clock signal having a respectivefrequency; and a second multiplexer, coupled to the second input and tothe second plurality of frequency dividers, to select as the storagedevice clock signal a divided clock signal having a respective frequencythat is closest to the storage device frequency from the divided clocksignals of the second plurality of frequency dividers.
 5. The clocksignal generator of claim 4, wherein the second multiplexer selects asthe storage device clock signal a divided clock signal having arespective frequency that is lowest of the respective frequencies of thedivided clock signals of the second plurality of frequency dividers whenthe electronic device is initializing.
 6. The clock signal generator ofclaim 1, wherein the electronic device is an Ethernet computer networkperipheral device coupled between a computer host system and a computernetwork, and wherein the base signal source is from the computer hostsystem, and wherein the storage device containing the value of the basefrequency is an EEPROM within the computer host system.
 7. The clocksignal generator of claim 1, wherein the electronic device is anEthernet computer network peripheral device coupled between a computerhost system and a computer network, and wherein the base signal sourceis from the computer network, and wherein the storage device containingthe value of the base frequency is an EEPROM within the computernetwork.
 8. A clock signal generator that generates a reference clocksignal having a reference frequency for an electronic device from a baseclock signal having a base frequency, the clock signal generatorcomprising:a first input, coupled to a base signal source that isexternal to the electronic device, for accepting the base clock signalfrom the base signal source; a second input, coupled to a storage devicethat is external to the electronic device, for accepting the value ofthe base frequency from the storage device; a plurality of frequencydividers, each frequency divider coupled to the first input for dividingthe base frequency of the base clock signal by a respective factor togenerate a respective divided clock signal having a respectivefrequency; and a multiplexer, coupled to the second input and to theplurality of frequency dividers, to select as the reference clock signala divided clock signal having a respective frequency that is closest tothe reference frequency from the plurality of divided clock signals;wherein the electronic device is an Ethernet computer network peripheraldevice coupled between a computer host system and a computer network,and wherein the base signal source is from the computer host system, andwherein the storage device containing the value of the base frequency isan EEPROM within the computer host system.
 9. A clock signal generatorthat generates a reference clock signal having a reference frequency foran electronic device from a base clock signal having a base frequency,the clock signal generator comprising:a first input, coupled to a basesignal source that is external to the electronic device, for acceptingthe base clock signal from the base signal source; a second input,coupled to a storage device that is external to the electronic device,for accepting the value of the base frequency from the storage device; aplurality of frequency dividers, each frequency divider coupled to thefirst input for dividing the base frequency of the base clock signal bya respective factor to generate a respective divided clock signal havinga respective frequency; and a multiplexer, coupled to the second inputand to the plurality of frequency dividers, to select as the referenceclock signal a divided clock signal having a respective frequency thatis closest to the reference frequency from the plurality of dividedclock signals; wherein the electronic device is an Ethernet computernetwork peripheral device coupled between a computer host system and acomputer network, and wherein the base signal source is from thecomputer network, and wherein the storage device containing the value ofthe base frequency is an EEPROM within the computer network.
 10. A clocksignal generator that generates a reference clock signal having areference frequency for an electronic device from a base clock signalhaving a base frequency, the clock signal generator comprising:a firstinput, coupled to a base signal source that is external to theelectronic device, for accepting the base clock signal from the basesignal source; a second input, coupled to a storage device that isexternal to the electronic device, for accepting the value of the basefrequency from the storage device; a plurality of frequency dividers,each frequency divider coupled to the first input for dividing the basefrequency of the base clock signal by a respective factor to generate arespective divided clock signal having a respective frequency; amultiplexer, coupled to the second input and to the plurality offrequency dividers, to select as the reference clock signal a dividedclock signal having a respective frequency that is closest to thereference frequency from the plurality of divided clock signal; and astorage device clock signal generator, coupled to the first input, thesecond input, and the storage device, for generating a storage deviceclock signal having a storage device frequency from the base clocksignal for reading the value of the base frequency from the storagedevice; wherein the storage device clock signal generator furtherincludes:a second plurality of frequency dividers, each of the secondplurality of frequency dividers coupled to the first input for dividingthe base frequency of the base clock signal by a respective factor togenerate a respective divided clock signal having a respectivefrequency; and a second multiplexer, coupled to the second input and tothe second plurality of frequency dividers, to select as the storagedevice clock signal a divided clock signal having a respective frequencythat is closest to the storage device frequency from the divided clocksignals of the second plurality of frequency dividers.
 11. The clocksignal generator of claim 10, wherein the second multiplexer selects asthe storage device clock signal a divided clock signal having arespective frequency that is lowest of the respective frequencies of thedivided clock signals of the second plurality of frequency dividers whenthe electronic device is initializing.
 12. A clock signal generator thatgenerates a first reference clock signal having a first referencefrequency and a second reference clock signal having a second referencefrequency for an Ethernet computer network peripheral device, coupledbetween a computer host system and a computer network, from a base clocksignal having a base frequency, the frequency generator comprising:afirst input, coupled to a base signal source that is part of thecomputer host system, for accepting the base clock signal from the basesignal source; a second input, coupled to an EEPROM that is part of thecomputer host system, for accepting the value of the base frequency fromthe EEPROM; a plurality of frequency dividers, each frequency dividercoupled to the first input for dividing the base frequency of the baseclock signal by a respective factor to generate a respective dividedclock signal having a respective frequency; a multiplexer, coupled tothe second input and to the plurality of frequency dividers, to selectas the first reference clock signal a first divided clock signal havinga first respective frequency that is closest to the first referencefrequency, and to select as the second reference clock signal a secondrespective divided clock signal having a second respective frequencythat is closest to the second reference frequency; and an EEPROM clocksignal generator, coupled to the first input, the second input, and theEEPROM, for generating an EEPROM clock signal having an EEPROM frequencyfrom the base clock signal for reading the value of the base frequencyfrom the EEPROM, the EEPROM clock signal generator further including:asecond plurality of frequency dividers, each of the second plurality offrequency dividers being coupled to the first input for dividing thebase frequency of the base clock signal by a respective factor togenerate a respective divided clock signal having a respectivefrequency; and a second multiplexer, coupled to the second input and tothe second plurality of frequency dividers, to select as the EEPROMclock signal a divided clock signal having a respective frequency thatis closest to the EEPROM frequency from the divided clock signals of thesecond plurality of frequency dividers.
 13. A clock signal generatorthat generates a reference clock signal having a reference frequency foran electronic device from a base clock signal having a base frequency,the clock signal generator comprising:a first input, coupled to one of avariety of a base signal source that is external to the electronicdevice, for accepting the base clock signal from the base signal source,wherein said base frequency of said base clock signal is variabledepending on said one of said variety of said base signal source towhich said first input is coupled; a second input, coupled to a storagedevice that is external to the electronic device, for accepting thevalue of the base frequency from the storage device, said storage devicecorresponding to said one of said variety of said base signal source towhich said first input is coupled; means for generating a plurality ofdivided clock signals by frequency dividing the base clock signal, eachdivided clock signal having a respective frequency; and means forselecting as the reference clock signal a divided clock signal having arespective frequency that is closest to the reference frequency, fromthe plurality of divided clock signals.
 14. The clock signal generatorof claim 13, further comprising:means for generating a storage deviceclock signal from the base clock signal for reading the value of thebase frequency from the storage device.
 15. A method for generating areference clock signal having a reference frequency for an electronicdevice from a base clock signal having a base frequency, the methodincluding the steps of:accepting the base clock signal from one of avariety of a base signal source that is external to the electronicdevice, wherein said base frequency of said base clock signal isvariable depending on said one of said variety of said base signalsource from which said base clock signal is accepted; accepting thevalue of the base frequency from a storage device that is external tothe electronic device, said storage device corresponding to said one ofsaid variety of said base signal source from which said base clocksignal is accepted; dividing the base frequency of the base clock signalby a plurality of factors to generate a plurality of divided clocksignals, each divided clock signal having a respective frequency; andselecting as the reference clock signal a divided clock signal having arespective frequency that is closest to the reference frequency, fromthe plurality of divided clock signals.
 16. The method of claim 15,wherein the step of selecting the reference clock signal furtherincludes the steps of:selecting as a first reference clock signal havinga first reference frequency a first divided clock signal having a firstrespective frequency that is closest to the first reference frequencyfrom the plurality of divided clock signals; and selecting as a secondreference clock signal having a second reference frequency a seconddivided clock signal having a second respective frequency that isclosest to the second reference frequency from the plurality of dividedclock signals.
 17. The method of claim 15, further comprising the stepof:generating a storage device clock signal having a storage devicefrequency from the base clock signal for reading the value of the basefrequency from the storage device.
 18. The method of claim 17, whereinthe step of generating the storage device clock signal further includesthe steps of:dividing the base frequency of the base clock signal by aplurality of factors to generate a second plurality of divided clocksignals, each divided clock signal having a respective frequency; andselecting as the storage device clock signal a divided clock signalhaving a respective frequency that is closest to the storage devicefrequency from the second plurality of divided clock signals.
 19. Themethod of claim 18, wherein the step of generating the storage deviceclock signal further includes the step of:selecting as the storagedevice clock signal a divided clock signal having a respective frequencythat is lowest of the second plurality of divided clock signals when theelectronic device is initializing.
 20. The method of claim 15, whereinthe electronic device is an Ethernet computer network peripheral devicecoupled between a computer host system and a computer network, andwherein the base signal source is from the computer host system, andwherein the storage device containing the value of the base frequency isan EEPROM within the computer host system.
 21. The method of claim 15,wherein the electronic device is an Ethernet computer network peripheraldevice coupled between a computer host system and a computer network,and wherein the base signal source is from the computer network, andwherein the storage device containing the value of the base frequency isan EEPROM within the computer network.
 22. A method for generating areference clock signal having a reference frequency for an electronicdevice from a base clock signal having a base frequency, the methodincluding the steps of:accepting the base clock signal from a basesignal source that is external to the electronic device; accepting thevalue of the base frequency from a storage device that is external tothe electronic device; dividing the base frequency of the base clocksignal by a plurality of factors to generate a plurality of dividedclock signals, each divided clock signal having a respective frequency;and selecting as the reference clock signal a divided clock signalhaving a respective frequency that is closest to the referencefrequency, from the plurality of divided clock signals; wherein theelectronic device is an Ethernet computer network peripheral devicecoupled between a computer host system and a computer network, andwherein the base signal source is from the computer host system, andwherein the storage device containing the value of the base frequency isan EEPROM within the computer host system.
 23. A method for generating areference clock signal having a reference frequency for an electronicdevice from a base clock signal having a base frequency, the methodincluding the steps of:accepting the base clock signal from a basesignal source that is external to the electronic device; accepting thevalue of the base frequency from a storage device that is external tothe electronic device; dividing the base frequency of the base clocksignal by a plurality of factors to generate a plurality of dividedclock signals, each divided clock signal having a respective frequency;and selecting as the reference clock signal a divided clock signalhaving a respective frequency that is closest to the referencefrequency, from the plurality of divided clock signals; wherein theelectronic device is an Ethernet computer network peripheral devicecoupled between a computer host system and a computer network, andwherein the base signal source is from the computer network, and whereinthe storage device containing the value of the base frequency is anEEPROM within the computer network.
 24. A method for generating areference clock signal having a reference frequency for an electronicdevice from a base clock signal having a base frequency, the methodincluding the steps of:accepting the base clock signal from a basesignal source that is external to the electronic device; accepting thevalue of the base frequency from a storage device that is external tothe electronic device; dividing the base frequency of the base clocksignal by a plurality of factors to generate a plurality of dividedclock signals, each divided clock signal having a respective frequency;selecting as the reference clock signal a divided clock signal having arespective frequency that is closest to the reference frequency, fromthe plurality of divided clock signals; and generating a storage deviceclock signal having a storage device frequency from the base clocksignal for reading the value of the base frequency from the storagedevice; wherein the step of generating the storage device clock signalfurther includes the steps of:dividing the base frequency of the baseclock signal by a plurality of factors to generate a second plurality ofdivided clock signals, each divided clock signal having a respectivefrequency; and selecting as the storage device clock signal a dividedclock signal having a respective frequency that is closest to thestorage device frequency from the second plurality of divided clocksignals.
 25. The method of claim 24, wherein the step of generating thestorage device clock signal further includes the step of:selecting asthe storage device clock signal a divided clock signal having arespective frequency that is lowest of the second plurality of dividedclock signals when the electronic device is initializing.